– Role: Design Verification Engineer – Qualification: B.E/B.Tech in ECE/EEE/CS/VLSI (M.Tech preferred) – Skills: C/C++, SystemVerilog, Python, EDA Tools – Location: Infra Silicon Team
– Role: Software Test & Automation Engineer – Eligibility: B.Tech/BS/MS (CS/IT/Engg) – Skills: C/C++/Python, Networking (TCP/IP, Protocols) – Experience: 0–2 years
– Role: Application Engineering Intern – Location: Bengaluru – Duration: 22–24 weeks (Jan 2026 onwards) – Eligibility: Final-year CS/IT Students (Graduating 2026) – Deadline: Sept 17, 2025